An interconnect in an integrated circuit distributes clock, regulatory and other signals as well as power or ground voltages to various components and circuits on a chip. The International Technology Roadmap for Semiconductors (ITRS) emphasizes the high speed transmission requirements on a chip as the driver for future interconnect development. Near term and long term interconnect requirements for microprocessors (MPs) and for dynamic random access memories (DRAMs) are outlined in the ITRS. MPs require local, intermediate and global wiring solutions and present both material and processing difficulties. Susceptibility of common interconnect metals t electromigration at high current densities (above 106 Amp/cm2) is a problem. Copper interconnect, introduced in 1998, is now routinely used, even with minimum feature size down to 130 nm. However, electrical resistivity of copper increases with decreasing dimensions and is attributed to scattering at surfaces and at grain boundaries. These size effects are due to interface roughness and by use of small grain sizes, which are hard to overcome and cannot be avoided by simply cooling to lower the resistivity. With reference to processing, present interconnect technology relies upon successful development of three processes: dry etching to create trenches and vias; deposition to fill metal plugs; and planarization. The aspect ratio of contact apertures is now 12:1 and may reach 23:1 by the year 2016. Creating high aspect ratio apertures with straight walls and uniform diameters using dry etching is an extremely difficult task and is expected to become progressively more difficult with each succeeding generation. HBr etching of SiO2 for a 9:1 aspect ratio contact hole has been found to provide a 135 nm diameter at one end and a 70 nm diameter at the other end of the hole by Hwang, Meyyappan, Mathod and Ranade, Jour. Vac. Sci. Technol. vol. 20B (2002) 2199. Aspect ratio-dependent etching becomes a serious problem with each new decrease in feature size. Plasma damage and cleaning of high aspect ratio features also pose concerns. Void-free filling of a high aspect ratio aperture is another concern.
Well known properties of CNTs, such as high current carrying capacity and material robustness, would make the CNTs ideally suited for use in electrical interconnects, if the fabrication problems could be resolved.
What is needed is a procedure or process sequence and associated system for providing an electrical interconnect, using an array of CNTs, that (1) provides reasonably uniform diameter CNTs with aspect ratios up to or higher than 100:1, (2) allows use of a variety of gap-filling insulating materials, (3) allows use of current densities of 106 Amps/cm2 and higher, (4) shows substantially no degradation at moderate or high current densities over long time intervals, and generally meets DRAM and microprocessor requirements.